ARM ARM1176JZF-S Instrukcja Użytkownika Strona 12

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Confidential
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The Instruction Pipeline
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The Instruction Pipeline
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The ARM7TDMI uses a 3-stage pipeline in order to increase the
speed of the flow of instructions to the processor
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Allows several operations to be performed simultaneously, rather than
serially
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The PC points to the instruction being fetched, not executed
§
Debug tools will hide this from you
§
This is now part of the ARM Architecture and applies to all processors
FETCH
DECODE
EXECUTE
Instruction fetched from memory
Decoding of registers used in instruction
Register(s) read from Register Bank
Shift and ALU operation
Write register(s) back to Register Bank
PC PC
PC - 4 PC-2
PC - 8 PC - 4
ARM Thumb
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