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Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-9
ID072410 Non-Confidential
10.3 ETM Programmers model
This section describes the mechanisms for programming the registers used to set up the trace
and triggering facilities of the macrocell. The programmers model enables you to use the ETM
registers to control the macrocell.
10.3.1 Modes of operation and execution
ETM-M3 implements ETMv3.5 for tracing 16-bit and 32-bit Thumb instructions. The
Embedded Trace Macrocell Architecture Specification describes the features of ETMv3.5.
See Features on page 10-2 for information on the trace features of the ETM-M3.
When the ETM is powered up or reset, you must program all of the registers that do not have an
architected reset state before you enable tracing. If you do not do so, the trace results are
Unpredictable.
When programming the ETM registers you must enable all the changes at the same time. To
achieve this, the Programming bit in ETMCR should be used. See Main Control Register,
ETMCR on page 10-11.
When the Programming bit is set to 0 you must not write to registers other than ETMCR,
because this can lead to Unpredictable behavior.
When setting the Programming bit, you must not change any other bits of ETMCR. You must
only change the value of bits other than the Programming bit of ETMCR when bit [1] of ETMSR
is set to 1. ARM recommends that you use a read-modify-write procedure when changing
ETMCR.
10.3.2 Register summary
Table 10-6 shows the ETM registers.
Table 10-6 ETM registers
Address Name Reset Type Description
0xE0041000
ETMCR
0x00000411
RW Main Control Register, ETMCR on page 10-11
0xE0041004
ETMCCR
0x8C802000
RO Configuration Code Register, ETMCCR on page 10-14
0xE0041008
ETMTRIGGER - RW Trigger Event Register.
See ARM Embedded Trace Macrocell Architecture Specification
0xE0041010
ETMSR - RW
ETM Status Register. See ARM Embedded Trace Macrocell
Architecture Specification
0xE0041014
ETMSCR
0x00020D09
RO System Configuration Register, ETMSCR on page 10-15
0xE0041020
ETMTEEVR - RW
TraceEnable Event Register. See ARM Embedded Trace Macrocell
Architecture Specification
0xE0041024
ETMTECR1 - RW TraceEnable Control 1 Register, ETMTECR1 on page 10-16
0xE0041028
ETMFFLR - RW
FIFOFULL Level Register. See ARM Embedded Trace Macrocell
Architecture Specification
0xE0041140
ETMCNTRLDVR1 - RW Free-running counter reload value
0xE00411E0
ETMSYNCFR
0x00000400
RO
Synchronisation Frequency Register. See ARM Embedded Trace
Macrocell Architecture Specification
- Technical Reference Manual 1
- Cortex-M3 2
- Contents 3
- List of Tables 5
- List of Figures 7
- • About this book on page x 9
- • Feedback on page xiii 9
- About this book 10
- Preface 11
- Other publications 12
- Feedback 13
- Chapter 1 14
- Introduction 14
- 1.1 About the processor 15
- 1.2 Features 16
- 1.3 Interfaces 17
- 1.4 Configurable options 18
- 1.5 Product documentation 19
- 1.6 Product revisions 22
- 0xE000ED14 23
- Chapter 2 25
- Functional Description 25
- 2.1 About the functions 26
- 2.2 Interfaces 28
- Chapter 3 31
- Programmers Model 31
- 3.3 Instruction set summary 34
- — STKALIGN bit to 1 40
- — UNALIGN_TRP bit to 1 40
- 3.4 System address map 41
- LDRH, STR, STRH 42
- 3.5 Write buffer 44
- 3.6 Exclusive monitor 45
- 3.7 Bit-banding 46
- Figure 3-2 Bit-band mapping 47
- 3.9 Exceptions 50
- Chapter 4 52
- System Control 52
- 4.1 About system control 53
- 4.2 Register summary 54
- 4.3 Register descriptions 56
- Chapter 5 58
- Memory Protection Unit 58
- 5.1 About the MPU 59
- 5.3 MPU programmers model 61
- Chapter 6 62
- 6.1 About the NVIC 63
- 6.3 NVIC programmers model 65
- Chapter 7 67
- 7.1 About debug 68
- 0xE000ED00 69
- 0xE00FF000 70
- 7.2 About the AHB-AP 72
- 7.3.2 FPB programmers model 76
- Chapter 8 77
- 8.1 About the DWT 78
- 8.3 DWT Programmers Model 80
- 0x40000000 81
- 0x4F000000 81
- 0x10000000 81
- 0x1F000000 81
- Chapter 9 82
- 9.1 About the ITM 83
- 9.3 ITM programmers model 85
- PRIVMASK 86
- Chapter 10 87
- 10.1 About the ETM 88
- Figure 10-1 ETM block diagram 89
- 10.2.9 Operation 94
- 10.3 ETM Programmers model 95
- Embedded Trace Macrocell 100
- ID072410 Non-Confidential 100
- Reserved 102
- 26 25 24 102
- Trace control enable 102
- Reserved, RAZ 106
- ETM powered up 106
- TRIGGER output value 107
- Chapter 11 109
- Trace Port Interface Unit 109
- 11.1 About the Cortex-M3 TPIU 110
- 11.3 TPIU programmers model 113
- TRIGGER input value 116
- Appendix A 122
- Revisions 122
- Glossary 129
- 0x00000000 132
- 0x1FFFFFFFF 132
- 0xE0040000 133
- 0xE00FFFFF 133
- 0x1FFFFFFF 133
- 0xE0000000 134
- 0xE003FFFF 134
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