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C bus interface RM0352

82/138 DocID024647 Rev 1

[3:2] STATUS: controller status. Valid for the operations MW, MR, WTS, RFS.

0: NOP: no operation is in progress

1: ON_GOING: an operation is ongoing

10: OK: the operation (OP field) has been completed successfully

11: ABORT: the operation (OP field) has been aborted due to the occurrence

of the event described in the CAUSE field.

[1:0] OP: operation

00: MW: master write operation

01: MR: master read operation

10: WTS: write to slave operation

11: RFS: read from slave operation

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 137 138

Reference manual 1
Contents 2
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List of tables 7
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List of figures 10
1 Referenced document 11
2 System and memory overview 12
2.2 Memory organization 13
2.3 Embedded SRAM 15
2.4 Flash memory overview 15
2.5 Physical remap 16
Interrupts RM0352 18
Table 3. Interrupt vectors 18
(continued) 18
5.1 Introduction 21
5.2 Clock generation 21
Figure 2. Clock generation 22
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5.3 Reset generation 24
5.3.2 Power-on reset 25
5.3.3 ECC reset 25
5.3.4 Watchdog reset 25
5.3.5 System reset request 26
5.3.6 Lockup reset 26
5.3.7 Recall done 26
6.3.4 Command register 34
MASS ERASE 34
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0-Unlocked 37
1NoLocked 37
1 Yes Unlocked 37
Watchdog timer (WDG) RM0352 40
Table 26. WDG register list 40
dual timer module (SP804) 47
8.2 Functional overview 48
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8.2.2 Functional description 50
Free running counter blocks 51
Interface reset 51
Prescaler operation 52
Timer operation 53
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Interrupt behavior 55
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8.3 Programmer's model 57
8.3.2 Register descriptions 59
Load register, TimerXLoad 60
". 63
9.4 Configuring SysTick 70
C bus interface RM0352 72
Table 70. I 72
C register list 72
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10.2.5 I 80
C status register (I2C_SR) 80
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11.1 Features 100
11.2 Clock prescaler 100
101
11.5.4 SSPRTINTR 114
11.5.1 SSPRXINTR 114
11.5.2 SSPTXINTR 114
11.5.3 SSPRORINTR 114
12.1 Features 115
12.2 IrDA SIR block 116
12.3 Baud rate generator 116
12.4 Interrupts 116
12.4.1 UARTMSINTR 117
12.4.2 UARTRXINTR 117
12.4.3 UARTTXINTR 117
12.5 UART registers 118
12.6 Register descriptions 120

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