ARM ARM7TDMI Instrukcja Użytkownika Pobierz pdf (Strona 39)

Page 35

4.39 UMLAL – Unsigned Multiply-Accumulate Long

Syntax:

UMLAL{<cond>}{S} <Rd_LSW>, <Rd_MSW>, <Rm>, <Rs>

RTL:

if(cond)

Rd_MSW:Rd_LSW  Rd_MSW:Rd_LSW + (Rs • Rm)

Flags updated if S used:

N, Z (V, C are unpredictable)

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 0 0 0 1 0 1 S Rd_MSW Rd_LSW Rs 1 0 0 1 Rm

Usage and Examples:

UMLAL performs an unsigned 32x32 multiply operation with a 64-bit accumulation. The

product of Rm and Rs is added to the 64-bit unsigned value contained in the register

pair Rd_MSW:Rd_LSW. All values are interpreted as unsigned binary.

The instruction below adds the product of R2 and R3 to the 64-bit number stored in

R1:0.

UMLAL R0, R1, R2, R3

4.40 UMULL – Unsigned Multiply Long

Syntax:

UMULL{<cond>}{S} <Rd_LSW>, <Rd_MSW>, <Rm>, <Rs>

RTL:

if(cond)

Rd_MSW:Rd_LSW  Rs • Rm

Flags updated if S used:

N, Z (V, C are unpredictable)

Encoding:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 0 0 0 0 1 0 0 S Rd_MSW Rd_LSW Rs 1 0 0 1 Rm

Usage and Examples:

UMULL performs an unsigned 32x32 multiply operation. The product of Rm and Rs is

stored as a 64-bit unsigned value in the register pair Rd_MSW:Rd_LSW. All values are

interpreted as unsigned binary.

The instruction below stores the product of R2 and R3 as a 64-bit number in R1:0.

UMULL R0, R1, R2, R3

1 2 ... 34 35 36 37 38 39 40 41 42 43

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