ARM Cortex R4F Instrukcja Użytkownika Pobierz pdf (Strona 40)

Exception/Interrupt Handler

Exception: a condition that needs to halt the normal sequential flow of

instruction execution.

Exception Categories: Reset, SVC Supervisor Call (Software

Interrupt), Fault (e.g., undefined op-code) and Interrupts

Each exception has:

• An exception number

• A priority level

• An exception handler routine (such as ISR)

• An entry in the vector table (address of associated ISR)

Exception Response

• Processor state (8 words) stored on stack: CPSR, Return Address, LR,

R12, R3 - R0. Allows a regular C function to be an ISR!

• Processor switched (from Thread Mode) to Handler Mode

(recorded in xPSR or CPSR).

• PC  vector table [exception # ]

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 63 64

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ARM Cortex R4F Instrukcja Użytkownika Strona 40