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Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-46
ID062813 Non-Confidential
Usage constraints There are no usage constraints.
Configurations Not applicable.
Attributes See Table 3-6 on page 3-13.
Figure 3-25 shows the bit assignments.
Figure 3-25 Test chip CFGREG47 Register bit assignments
Table 3-27 shows the bit assignments.
31 8 0
0 00000 0 000000011100 0000 110000 00
318
0
12
Reserved
AWAP_S1
ARAP_S1
AWAP_S0
ARAP_S0
CWAKEUP_M0
CWAKEUP_S1
AWREGIONS4[3:0]
23 22 19 417 16 1521 20 11 7
CWAKEUP_S0
ARREGIONS4[3:0]
AWREGIONS3[3:0]
ARREGIONS3[3:0]
Table 3-27 Test chip CFGREG47 Register bit assignments
Bits Name Function
[31:23] - Reserved. Do not modify.
[22] AWAP_S1 DMC-400 S1 port write auto pre-charge policy signal:
b0
b1
The default is
b0
.
[21] ARAP_S1 DMC-400 S1 port read auto pre-charge policy signal:
b0
b1
The default is
b0
.
[20] AWAP_S0 DMC-400 S0 port write auto pre-charge policy signal:
b0
b1
The default is
b0
.
[19] ARAP_S0 DMC-400 S0 port read auto pre-charge policy signal:
b0
b1
The default is
b0
.
[18] CWAKEUP_M0 Disables DMC-400 M0 port clock gating.
b0
Enables M0 port clock gating.
b1
Disables M0 port clock gating.
The default is
b1
.
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