ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 46)

Hardware Description

ID062813 Non-Confidential

The test chip contains seven PLLs. They use the programmable clocks from the daughterboard

to generate some of the clocks that the internal systems on the test chip use. See Figure 2-10 on

page 2-26.

The SCC registers control the output frequency of each PLL. Control bits from the registers set

the PLL dividers to the values that achieve the required output frequency.

Two SCC registers control each PLL and send a:

• 6-bit word, CLKR, to the input divider.

• 13-bit word CLKF to the feedback divider.

• 4-bit word CLKOD to the output divider.

The following equation provides the output frequency of each PLL:

Figure 2-11 shows the structure of the test chip PLLS, A15 PLL0, and A7 PLL0 that have

divide-by-two blocks on their outputs.

Figure 2-11 Structure of the test chip PLLs A15 PLL0 and A7 PLL0

Registers CFGREG19 and CFGREG20 control the dividers of A15 PLL0 that generates

CPU_CLK0_A15 and CPU_CLK0_A15/2.

Registers CFGREG23 and CFGREG24 set the dividers of A7 PLL0 that generates

CPU_CLK2_A7 and CPU_CLK2_A7/2.

Registers CFGREG21 and CFGREG22 set the dividers of A15 PLL1 that generates

CPU_CLK1_A15.

Registers CFGREG25 and CFGREG26 set the dividers of A7 PLL1 that generates

CPU_CLK3_A7.

Registers CFGREG17 and CFGREG18 set the dividers of HDLCD PLL that generates

PXLCLK.

Note

The configuration process bypasses HDLCD PLL by default.

Registers CFGREG15 and CFGREG16 set the dividers of DDR PLL that generates DDRCLK.

Registers CFGREG13 and CFGREG14 set the dividers of SYSPLL that generates SYSCLK.

Figure 2-12 on page 2-32 shows the structure of SYS PLL that has three programmable dividers

on its output.

Output frequency = Input frequency x

(CLKF + 1)

(CLKOD + 1) (CLKR + 1)x

CPU PLL

VCO

Divide by CLKF+1

Divide by CLKOD+1

Divide by CLKR+1

PLL Value Register[5:0] = CLKR

PLL Control Register[28:16] = CLKF

PLL Value Register[11:8] = CLKOD

CPUREFCLK0

CPU_CLK0_A15

CPUREFCLK2

CPU_CLK2_A7

÷2

CPU_CLK0_A15/2

CPU_CLK0_A7/2

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 177 178

Komentarze do niniejszej Instrukcji

Brak uwag

ARM AMBA NIC-301 Dokumentacja Strona 46

Komentarze do niniejszej Instrukcji