ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 149)

Signal Descriptions

ID062813 Non-Confidential

A.2 HDRX HSB multiplexing scheme

A bus multiplexing scheme is necessary to reduce the number of pins required on the HDRX

header for the 64-bit AXI master on the HSBM bus. The LogicTile Express daughterboard must

implement a similar multiplexing scheme to be compatible with the CoreTile Express signals.

OSCCLK 4 on the CoreTile Express A15×2 daughterboard generates the AXI master bus clock.

This clocks the test chip master multiplex and demultiplex logic. This logic is positive- and

negative-edge triggered to avoid the requirement for a PLL or double-rate clock in the test chip.

Double edge clocking also enables operation at low speed for use with emulation systems.

Note

All signals on the HSB (M) bus are 1.8V.

Figure A-2 shows a simplified block diagram of the multiplexing scheme for the AXI bus.

Figure A-2 HSB multiplexing

Application notes AN283, Example LogicTile

™

Express 3MG Design for a CoreTile

™

Express

A15×2, and AN305, Example LogicTile

™

Express 13MG Design for a CoreTile

™

Express

A15×2, provided by ARM, implement example AMBA systems using a LogicTile Express

CoreTile Express A15x2 A7x3

Daughterboard

LogicTile Express

FPGA Daughterboard

HDRX

Motherboard Express uATX

HDRX1 HDRX2

HDRX

Cortex-A15_A7 Test Chip

Mux/Demux

NIC-301 interconnect fabric

Async Master

OSCCLK

X[79:0]

XP049

Mux/Demux

AXI S

CLK

Logic

Site 1 Site 2

HSB (M)

AXI M

HSB (S)

AXI M

(CLK)

AXI S

(CLK)

HSBM

(CLK)

HSBS

(CLK)

FPGA

1 2 ... 144 145 146 147 148 149 150 151 152 153 154 ... 177 178

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