ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 73)

Programmers Model

ID062813 Non-Confidential

In each register:

• Bits[31:24] and bits[15:8] are the match bits.

• Bits[23:16] and bits[7:0] are the mask bits.

The 8 match bits modified by the 8 mask bits represent the 7

and 8

digits of the SMC base

address as follows:

in mask register

Masked. Corresponding bit in match register is Don’t Care, X.

in mask register

Not masked. Corresponding bit in match register is unchanged.

Example 3-1 Defining SMC CS4 base address

The match bits of SMC CS4 base address are

b00001100

, and the mask bits are

b11111100

. See

Test chip SCC Register 2 on page 3-18. The result of the mask operation is

b000011XX

This means that the 8

and 7

digits of the base address of SMC CS4 have the value

0x0C

. Test

chip circuitry generates the address range of SMC CS4 as

0x00_0C00_0000

0x00_0FFF_FFFF

that is a range of 64MB. See Figure 3-1 on page 3-4 and Table 3-1 on page 3-5.

Example 3-2 Defining SMC CS0 base address

The match bits of SMC CS0 base address are

b00000000

, and the mask bits are

b11110100

. See

Test chip SCC Register 0 on page 3-17. The result of the mask operation is

b0000X0XX

This means the 8

and 7

digits of the base address of SMC CS0 have two values that are

0x00

and

0x08

. Test chip circuitry generates the address ranges of SMC CS0 as

0x00_0000_0000

0x00_03FF_FFFF

and

0x00_0800_0000

0x00_0BFF_FFFF

. Each range is 64MB. See Figure 3-1 on

page 3-4 and Table 3-1 on page 3-5

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 177 178

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