ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 45)

Hardware Description

ID062813 Non-Confidential

The clock generators have an absolute accuracy of better than 1%. If you enter a setting that

cannot be precisely generated, the value is approximated to the nearest usable value.

2.7.3 Test chip PLLs and clock divider logic

This section describes the test chip PLLs and dividers that generate the internal clocks that drive

the on-chip systems.

DDRREFCLK DDR2 PLL

reference clock

OSCCLK 8 20MHz-50MHz

Default is 50MHz

Reference for DDRCLK. This is the default clock for

the DMC-400 memory interface and DDR2 physical

interface (PHY), the DDR2 pad interface. This

operates asynchronously to the AXI clock, ACLK.

See Figure 2-15 on page 2-39.

Default DDRCLK to OSCCLK 8 ratio: 8:1.

Note

You can also select SYSREFCLK as the reference

clock for the DDR2 PLL. See Test chip SCC Register

11 on page 3-27.

ARM does not recommend the non-default option,

and Figure 2-10 on page 2-26 does not show this

non-default connection.

PXLREFCLK HDLCD PLL

reference clock

OSCCLK 5 23.75MHz-165MHz

Default is

23.75MHz

Reference for PXLCLK, the HDLCD controller

clock in the test chip. You must adjust the frequency

of this clock to match your target screen resolution.

The HDLCD controller is capable of displaying up to

1920×1080p pixel resolution at 60Hz with PXLCLK

set to 165MHz.

The configuration process bypasses the HDLCD PLL

by default. See:

• Figure 2-10 on page 2-26

• Test chip SCC Registers 13, 15, 17, 19, 23, and

25 PLL control registers on page 3-31

• Appendix B HDLCD controller.

Note

You can also select SYSREFCLK as the reference

clock for the HDLCD PLL. See Test chip SCC

ARM does not recommend the non-default option,

and Figure 2-10 on page 2-26 does not show this

non-default connection.

SMB_REFCLK SMB clock OSCCLK 6 15MHz-40MHz

Default is 40MHz

Static memory controller clock.

REFCLK24MHZ Reference

clock

OSCCLK 6 Default is 24MHz System timer, system counter, and SP805 Watchdog

Timer clock.

Table 2-9 Daughterboard OSCCLK clock sources (continued)

Test chip signal Function Source

OSCCLK

frequency

range and default

Description, clocks derived from test chip

signal

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 177 178

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