ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 79)

Programmers Model

ID062813 Non-Confidential

Figure 3-10 Test chip CFGREG5 Register bit assignments

Table 3-12 shows the bit assignments.

Test chip SCC Register 6

The CFGREG6 Register characteristics are:

Purpose Reset control register that enables you to read and write test chip resets.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-11 shows the bit assignments.

Figure 3-11 Test chip CFGREG6 Register bit assignments

000 0000000000000 100000000000000 0

DMA_BOOT_ADDR

Table 3-12 Test chip CFGREG5 Register bit assignments

Bits Name Function

[31:0] DMA_BOOT_ADDR Boot address for DMAC. This configures the address location that contains

the first instruction that the DMAC executes when it exits from reset.

Note

The DMAC uses this address only when DMA_BOOT_FRM_PC is HIGH.

See Test chip SCC Register 4 on page 3-19.

See the AMBA

DMA Controller DMA-330 Technical Reference Manual.

31 28 27 26 13 12 9 8 7 6 3 0

00 1 1 11111 1111111 1 111111111111

01 1

25 54 121011

DDR_PHY_IDDQ

DDR_PHY_RESET_N

A7_NDBGPRESET[2:0]

A7_NL2RESET

A7_NCORERESET[2:0]

A7_NCOREPORESET[2:0]

A15_NDBGRESET[1:0]

A15_NCXRESET[1:0]

Reserved

A7_NVSOC_RESET

A7_NVCORERESET

A7_NSOCDBGRESET

24 22 21

A7_ETMRESET[2:0]

18 16 15

Reserved

A15_NVSOC_RESET

A15_NVCORERESET

A15_NPRESETDBG

A15_NL2RESET

A15_NCORERESET[1:0]

A15_NCOREPORESET[1:0]

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 177 178

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