ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 105)

Programmers Model

ID062813 Non-Confidential

Figure 3-26 Test chip CFGREG48 Register bit assignments

Table 3-28 shows the bit assignments.

31 0

0 00000 0 000000000000 0011 010000 11

216

24 23 20 19 1528 14 13 12 11 10

NONBOOT_CLUSTER_PWRDWN_ENABLE

PM_PERCORE_MBOX_ENABLE

BOOT_CLUSTER[3:0]

CLUSTER1_NUM_CPU[3:0]

ACTIVE_CLUSTER[1:0]

CLUSTER0_NUM_CPU[3:0]

CA7_EVENTSTREAM

BOOT_CPU[3:0]

CA15_EVENTSTREAM

CA15_WFE_NOP_ENABLE

Reserved

29 1

Table 3-28 Test chip CFGREG48 Register bit assignments

Bits Name Function

[31:29] - Reserved. Do not modify.

[28] BOOT_CLUSTER Denotes the boot cluster:

CA7 cluster.

CA15 cluster.

The default is

[27:26] - Reserved. Do not modify.

[25:24] BOOT_CPU[1:0] Denotes the boot core:

b10

CA7 core 2.

b01

CA15 core 1 or CA7 core 1.

b00

CA15 core 0 or CA7 core 0.

The default is

b00

[23:20] CLUSTER1_NUM_CPU[3:0] Denotes the number of cores present in the Cortex-A7 cluster.

The default is

b0011

and this indicates that three Cortex-A7

cores are present.

[19:16] CLUSTER0_NUM_CPU[3:0] Denotes the number of cores present in the Cortex-A15

cluster.

The default is

b0010

and this indicates that two Cortex-A15

cores are present.

1 2 ... 100 101 102 103 104 105 106 107 108 109 110 ... 177 178

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