ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 75)

Programmers Model

ID062813 Non-Confidential

Figure 3-6 Test chip CFGREG1 Register bit assignments

Table 3-8 shows the bit assignments.

Test chip SCC Register 2

The CFGREG2 Register characteristics are:

Purpose SMC CS4 and CS5 Register that enables you to read and write match and

mask bits for the SMC CS4. See Mask operation to define SMC chip select

address ranges on page 3-15. SMC CS5 is reserved and the match and

mask bits for CS5 are also reserved.

Usage constraints Bits[31:16] are reserved. Do not write to or read these bits.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-7 shows the bit assignments.

Figure 3-7 Test chip CFGREG2 Register bit assignments

Table 3-9 shows the bit assignments.

SMC_ADDR_MATCH0_3

31 24 23 16 15 8 0

0 11100 1 1100011111100 1111 100000

SMC_ADDR_MASK0_3

SMC_ADDR_MATCH0_2

SMC_ADDR_MASK0_2

Table 3-8 Test chip CFGREG1 Register bit assignments

Bits Name Function

[31:24] SMC_ADDR_MATCH0_3 SMC CS3 address match of top 8 bits

[23:16] SMC_ADDR_MASK0_3 SMC CS3 address mask of top 8 bits

[15:8] SMC_ADDR_MATCH0_2 SMC CS2 address match of top 8 bits

[7:0] SMC_ADDR_MASK0_2 SMC CS2 address mask of top 8 bits

31 16 15 8 0

0 10000 1 0110011111100 1111 100000

Reserved

SMC_ADDR_MATCH1_0

SMC_ADDR_MASK1_0

Table 3-9 Test chip CFGREG2 Register bit assignments

Bits Name Function

[31:24] - Reserved. Do not modify.

1 2 ... 70 71 72 73 74 75 76 77 78 79 80 ... 177 178

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