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Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-29
ID062813 Non-Confidential
[13:11] PCLKRATIO[2:0] PCLK divider ratio. This divides the output of SYS PLL to derive PCLK.
b000
Divider ratio 1.
b001
Divider ratio 2.
b010
Divider ratio 3.
b011
Divider ratio 4.
All other bit combinations are invalid. The default is
b001
. See Figure 2-10 on page 2-26,
Figure 2-12 on page 2-32, and Table 2-9 on page 2-28.
Note
The maximum operating frequency of PCLK is 1GHz.
[10:8] ACLKRATIO[2:0] ACLK divider ratio: This divides the output of SYS PLL to derive ACLK.
b000
Divider ratio 1.
b001
Divider ratio 2.
b010
Divider ratio 3.
b011
Divider ratio 4.
All other bit combinations are invalid. The default is
b001
. See Figure 2-10 on page 2-26,
Figure 2-12 on page 2-32, and Table 2-9 on page 2-28.
Note
The maximum operating frequency of ACLK is 500MHz.
[7:6] - Reserved. Do not modify.
[5] A7_1_REFCLK_SELECT Selects the reference clock to A7 PLL 1:
b0
Selects CPUREFCLK3 as input reference for A7 PLL 1.
b1
Selects SYSREFCLK as input reference for A7 PLL 1.
The default is
b0
. See Figure 2-10 on page 2-26 and Table 2-9 on page 2-28.
Note
ARM does not recommend the non-default option, and Figure 2-12 on page 2-32 does not
show this non-default connection.
[4] A7_0_REFCLK_SELECT Selects the reference clock to A7 PLL 0:
b0
Selects CPUREFCLK2 as input reference for A7 PLL 0.
b1
Selects SYSREFCLK as input reference for A7 PLL 0.
The default is
b0
. See Figure 2-10 on page 2-26 and Table 2-9 on page 2-28.
Note
ARM does not recommend the non-default option and Figure 2-12 on page 2-32 does not
show this non-default connection.
[3] A15_1_REFCLK_SELECT Selects the reference clock to A15 PLL 1:
b0
Select CPUREFCLK1 as input reference for A15 PLL 1.
b1
Select SYSREFCLK as input reference for A15 PLL 1.
The default is
b0
. See Figure 2-10 on page 2-26 and Table 2-9 on page 2-28.
Note
ARM does not recommend the non-default option and does Figure 2-10 on page 2-26 not
show this non-default connection.
Table 3-17 Test chip CFGREG11 Register bit assignments (continued)
Bits Name Function
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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