
Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-70
ID062813 Non-Confidential
System counter read register descriptions
The following sections describes the system counter read registers.
CNTCVL
The CNTCVL Register characteristics are:
Purpose System counter lower 32 bits read register that enables you to read the
system counter lower 32 bits.
Usage constraints This register is read-only.
Configurations Not applicable.
Attributes See Table 3-56 on page 3-69.
Figure 3-41 shows the bit assignments.
Figure 3-41 System counter CNTCVL Read Register bit assignments
Table 3-57 shows the bit assignments.
CNTCVU
The CNTCVU Register characteristics are:
Purpose System counter upper 32 bits read register that enables you to read the
system counter upper 32 bits.
Usage constraints This register is read-only.
0xFF0
COMPID0 RO
0x0000_000D
32 System counter Component Identification read register 0.
See COMPID0 on page 3-73.
0xFF4
COMPID1 RO
0x0000_00F0
32 System counter Component Identification read register 1.
See COMPID1 on page 3-74.
0xFF8
COMPID2 RO
0x0000_0005
32 System counter Component Identification read register 2.
See COMPID2 on page 3-74.
0xFFC
COMPID3 RO
0x0000_00B1
32 System counter Component Identification read register 3.
See COMPID3 on page 3-75.
Table 3-56 System counter read register summary (continued)
Offset Name Type Test chip reset Width Description
31 0
0 00000 0 000000000000 0000 000000 00
0
CNTCVL
Table 3-57 System counter CNTCVL Read Register bit assignments
Bits Name Function
[31:0] CNTCVL Current unencoded value of counter lower 32 bits, CNTCV[31:0].
The default is
0x0000_0000
.
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