ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 99)

Programmers Model

ID062813 Non-Confidential

Test chip SCC Register 45

The CFGREG45 Register characteristics are:

Purpose Cache Coherency Interconnect, CCI-400, configuration register 0 that

defines the decode of each region of the address map. One set of inputs

exists for each of the 16 regions in the address map.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-23 on page 3-43 shows the bit assignments.

[14] SYSBARDISABLE Disables broadcasting barriers onto system bus:

Enables broadcast barriers onto system bus. This requires an AMBA4

interconnect.

Disables broadcast barriers onto system bus. This is compatible with an

AXI3 interconnect.

The default is

[13] ACINACTM Disables Cortex-A7 snoop interface:

ACP snoop interface enabled.

ACP snoop interface disabled.

The default is

[12] L2RSTDISABLE Disables automatic L2 cache invalidate at reset:

Hardware resets L2 cache.

Hardware does not reset L2 cache.

The default is

[11] - Reserved. Do not modify.

[10:8] L1RSTDISABLE[2:0] Disables automatic L1 cache invalidate at reset:

Hardware resets L1 cache.

Hardware does not reset L1 cache.

The default is

b000

[7] - Reserved. Do not modify.

[6:4] CP7SDISABLE[2:0] Disables write to secure Cortex-A7 core registers:

Enables write to secure A7 core registers.

Disables write to secure A7 core registers.

The default is

b000

[3] - Reserved. Do not modify.

[2:0] SPNIDEN[2:0] Maps to the SPNIDEN secure non-invasive debug enable bus for all three Cortex-A7

cores:

Disables secure debug.

Enables secure debug.

The default is

b111

Table 3-24 Test chip CFGREG44 Register bit assignments (continued)

Bits Name Function

1 2 ... 94 95 96 97 98 99 100 101 102 103 104 ... 177 178

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