ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 97)

Programmers Model

ID062813 Non-Confidential

Table 3-23 shows the bit assignments.

Table 3-23 Test chip CFGREG43 Register bit assignments

Bits Name Function

[31] - Reserved. Do not modify.

[30:28] SPIDEN[2:0] Maps to the SPIDEN secure privileged invasive debug enable bus

for all three Cortex-A7 cores:

Disables secure privileged invasive debug.

Enables secure privileged invasive debug.

The default is

b111

[27] - Reserved. Do not modify.

[26:24] NIDEN[2:0] Maps to the NIDEN non-invasive debug enable bus for all three

Cortex-A7 cores:

Disables non-invasive debug.

Enables non-invasive debug.

The default is

b111

[23] - Reserved. Do not modify.

[22:20] DBGEN[2:0] Maps to the DBGEN invasive debug enable bus for all three

Cortex-A7 cores:

Disables invasive debug.

Enables invasive debug.

The default is

b111

[19] - Reserved. Do not modify.

[18:16] CFGTE[2:0] Maps to the Thumb Exception Enable bus for all three Cortex-A7

cores. This bit sets:

Exception, including reset, taken in ARM state.

Exception, including reset, taken in Thumb state.

The default is

b000

[15] - Reserved. Do not modify.

[14:12] VINITHI_CORE[2:0] Location of exception vectors at reset for all three Cortex-A7 cores:

Exception vectors start at address

0x0000_0000

Exception vectors start at address

0xFFFF_0000

The default is

b000

[11] - Reserved. Do not modify.

[10:8] CFGEND[2:0] Maps to the CFGEND[2:0] bus. Configures cores as bigend:

: Configures cores as little-end.

: Configures cores as big-end.

The default is

b000

[7:4] - Reserved. Do not modify.

[3:0] CLUSTER_ID Maps to the CLUSTERID[3:0] bus.

1 2 ... 92 93 94 95 96 97 98 99 100 101 102 ... 177 178

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