ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 30)

Hardware Description

ID062813 Non-Confidential

Figure 2-7 CoreTile Express A15×2 A7×3 daughterboard configuration and reset timing cycle

Configuration and reset signals

Table 2-1 shows the Cortex-A15_A7 MPCore test chip configuration and reset signals:

Run

configure

IOFPGA

ready

CB_nPO

CB_nRST

CB_RSTRE

Cold

reset

Warm

reset

Run

Cold/Warm

reset

ICE or

Soft reset

IOFPGA

MBM_nRST

CB_READY

SPI

configure

Daughterboard

Configuration Controller

reset ready

CB_OK

CB_CFGnRS

On/Off/Soft

reset button

Either a soft reset from

motherboard or a reset

request from

daughterboard

1234 5678910

Table 2-1 Configuration and reset signals

Reset source Destination Description

CB_CFGnRST

Daughterboard

Configuration

Controller

Initiate the daughterboard configuration process.

CB_OK MCC Daughterboard configuration system ready.

CB_SSPx

Daughterboard

Configuration

Controller

-MCC

Signal transactions during time period 3, DB configuration, that cause the

Daughterboard Configuration Controller to configure the Cortex-A15 MPCore

test chip SCC registers and daughterboard OSCCLKs.

CB_READY MCC Daughterboard configured and ready.

The PLLS_LOCKED

signal and the control signals

between the Daughterboard

Configuration Controller

, Cortex-A15 MPCore test chip, and the daughterboard

OSCLCLKS indicate to the

Daughterboard Configuration Controller and MCC

that the PLLs are locked and that the daughterboard OSCCLKS are operating.

CB_nPOR Test chip internal

signal nPORESET

This is the main power-on-reset that resets the entire test chip logic and the clock

generation logic except for the PLLs.

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