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HDLCD controller
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. B-13
ID062813 Non-Confidential
Attributes See Table B-1 on page B-3.
Figure B-11 shows the bit assignments.
Figure B-11 Vertical Synch Width Register bit assignments
Table B-12 shows the bit assignments.
Vertical Back Porch Width Register
The V_BACK_PORCH Register characteristics are:
Purpose Holds the width of the interval between the vertical sync and the first
visible line, counted in number of horizontal scan lines.
Usage constraints There are no usage constraints.
Configurations Available in all HDLCD controller configurations.
Attributes See Table B-1 on page B-3.
Figure B-12 shows the bit assignments.
Figure B-12 Vertical Back Porch Width Register bit assignments
Table B-13 shows the bit assignments.
Vertical Data Width Register
The V_DATA Register characteristics are:
Purpose Holds the width of the vertical data area, that is, the number of visible
lines, counted in the number of horizontal scan lines.
Usage constraints There are no usage constraints.
31 12 11 0
Reserved V_SYNC
Table B-12 Vertical Synch Register bit assignments
Bits Name Function
[31:12] - Reserved, write as zero, read undefined
[11:0] V_SYNC Vertical synch width -1
31 12 11 0
Reserved V_BACK_PORCH
Table B-13 Vertical Back Porch Register bit assignments
Bits Name Function
[31:12] - Reserved, write as zero, read undefined
[11:0] V_BACK_PORCH Vertical back porch width -1
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