ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 40)

Hardware Description

ID062813 Non-Confidential

Figure 2-9 System clocks overview

Note

The CoreTile Express A15×2 A7×3 daughterboard derives MMB clocks from PXLREFCLK,

that originates from OSC 5 on the daughterboard. See Figure 2-10 on page 2-26.

Figure 2-10 on page 2-26 shows a functional view of the CoreTile Express A15×2 A7×3

daughterboard clocks, and the internal test chip PLLs and clocks.

Motherboard Express μATX

V2M-P1

CoreTile Express A15x2 A7X3

Daughterboard

LogicTile Express

FPGA Daughterboard

Cortex-A15_A7

Test Chip

Daughterboard

Configuration

Controller

FPGA

CPUREFCLK0_A7

PXLREFCLK

HDRY HDRX

MCC

HDRY1

HDRY

HDRY2HDRX1

HDRX

HDRX2

SMB_CLKI

IO and multiplexer FPGAs

PCI-Express

clock

generator

Clock generators

To PCI-Express sitesTo peripherals

OSCCLKS

FPGA ref clocks

DDR2

SDRAM

Site 1 Site 2

SYSREFCLK

CPUREFCLK1_A7

CPUREFCLK0_A15

CPUREFCLK1_A15

SMBREFCLK

DDRREFCLK

MMB_IDCLK

SMB_CLKO

DDR clocks

SMB feedback

SMB_CLKO

PCI ref clock

MMB clocks

HSBM (CLK)

Daughterboard

Configuration

Controller

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 177 178

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