ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 47)

Hardware Description

ID062813 Non-Confidential

Figure 2-12 Structure of the test chip PLL SYS PLL

The PCLK programmable divider default divide ratio is 2:1.

The TRACECLKIN default divide ratio is 4:1.

The ACLK default divide ratio is 2:1.

See the following for information on how to control the PLL dividers:

• Test chip SCC Registers 13, 15, 17, 19, 23, and 25 PLL control registers on page 3-31

• Test chip SCC Registers 14, 16, 18, 22, 24 and 26 PLL value registers on page 3-33.

See Test chip SCC Register 11 on page 3-27 for information on how to control the

programmable dividers on the output of SYS PLL.

2.7.4 External clocks

Table 2-10 shows the external clocks that connect between the CoreTile Express A15×2 A7×3

daughterboard and the motherboard, and between the CoreTile Express A15×2 A7×3

daughterboard and the optional FPGA daughterboard in Site 2.

CPU PLL

VCO

Divide by CLKF+1

Divide by CLKOD+1

Divide by CLKR+1

SYS_PLL_Value Register[5:0] = CLKR

SYS_PLL_Control Register[28:16] = CLKF

SYS_PLL_Value Register[11:8] = CLKOD

SYSREFCLK

SYSCLK

Prog

divider

PCLK

Prog

divider

Prog

divider

TRACECLKIN

ACLK

Table 2-10 External clock sources

Test chip signal Function Source

Frequency range

and default

Description

HSBM (CLK) --- See Table 2-9 on page 2-28.

MMB_IDCLK MMB clock OSCCLK 5 23.75MHz-166MHz

Default is 23.7MHz

Clock for HDLCD 24-bit RGB data and

synchronization signals.

See PXLREFCLK in Table 2-9 on

page 2-28.

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 177 178

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