
Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-27
ID062813 Non-Confidential
Figure 3-14 Test chip CUSTOMER_ID Register bit assignments
Table 3-16 shows the bit assignments.
Figure 3-14 and Table 3-16 show a test chip that has revision number r0p0, designer ID 41, for
ARM, and part number
0x002
, for LPAE.
Test chip SCC Register 11
The CFGREG11 Register characteristics are:
Purpose Clock control register that enables you to read and write the bits that
control clocks dividers, and selects the inputs to PLLs.
Usage constraints Some bit combinations are invalid. See Table 3-17 on page 3-28.
Configurations Not applicable.
Attributes See Table 3-6 on page 3-13.
Figure 3-15 on page 3-28 shows the bit assignments.
31 0
0 10000 0 1000000000000 0000 100000 10
CONFIGURATION
24 23 1228 27
MAJOR_REVISION_RN
MINOR_REVISION_RN
20 19 11
DESIGNER_ID
PART_NUMBER
Table 3-16 Test chip CUSTOMER_ID Register bit assignments
Bits Name Function
[31:28] - Cortex-A15_A7 test chip configuration
[27:24] - Cortex-A15_A7 test chip major revision number
[23:20] - Cortex-A15_A7 test chip minor revision number
[19:12] - Cortex-A15_A7 test designer
[11:0] - Cortex-A15_A7 part number
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