ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 85)

Programmers Model

ID062813 Non-Confidential

Figure 3-15 Test chip CFGREG11 Register bit assignments

Table 3-17 shows the bit assignments.

31 20 13 8 7 3 0

000 0010001000011 010010000000000 0

24 54 12101417

TRACECLKINRATIO[2:0]

PCLKRATIO[2:0]

ACLKRATIO[2:0]

A7_1_REFCLK_SELECT

HDLCD_REFCLK_SELECT

DDR_REFCLK_SELECT

Reserved

23 16

28 27

A7_CLK_SEL[3:0]

A15_CLK_SEL[3:0]

Reserved

A7_0_REFCLK_SELECT

A15_1_REFCLK_SELECT

A15_0_REFCLK_SELECT

Table 3-17 Test chip CFGREG11 Register bit assignments

Bits Name Function

[31:28] - Reserved. Do not modify.

[27:24] A7_CLK_SEL[3:0] Selects the source for A7_ CLK:

b0001

Selects CPU_CLK0_A7.

b0010

Selects CPU_CLK1_A7.

b0100

Selects SYSCLK.

b1000

Selects CPU_CLK0_A7/2.

All other bit combinations are invalid.

The default is

b0001

. See Figure 2-10 on page 2-26.

[23:22] A15_CLK_SEL[3:0] Selects the source for A15_ CLK:

b0001

Selects CPU_CLK0_A15.

b0010

Selects CPU_CLK1_A15.

b0100

Selects SYSCLK.

b1000

Selects CPU_CLK0_A15/2.

All other bit combinations are invalid.

The default is

b0001

. See Figure 2-10 on page 2-26.

[19:17] - Reserved. Do not modify.

[16:14] TRACECLKINRATIO[2:0] TRACECLKIN divider ratio. This divides the output of SYS PLL to derive

TRACECLKIN:

b000

Divider ratio 1.

b001

Divider ratio 2.

b010

Divider ratio 3.

b011

Divider ratio 4.

All other bit combinations are invalid. The default is

b011

. See Figure 2-10 on page 2-26,

Figure 2-12 on page 2-32, and Table 2-9 on page 2-28.

Note

The maximum operating frequency of TRACECLKIN is 140MHz.

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 177 178

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