ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 82)

Programmers Model

ID062813 Non-Confidential

Note

When power-management is enabled in the

board.txt

file, the CA15 and CA7 cores must not

directly write to CFGREG6 or CFGREG11 because the Daughterboard Configuration

Controller controls this. Writing to these registers prevents the power-management interface

from functioning correctly.

Test chip SCC Register 7

The CFGREG7 Register characteristics are:

Purpose Enables you to read the DAP ROM default target ID.

Usage constraints This register is read-only.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-12 shows the bit assignments.

Figure 3-12 Test chip CFGREG7 Register bit assignments

[5:4] A15_NCXRESET[1:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b11

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

[3:2] A15_NCORERESET[1:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b11

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

[1:0] A15_NCPURESET[1:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b11

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

Note

The Cortex

-A15 Technical Reference Manual names this signal as nCPUPORESET.

Table 3-13 Test chip CFGREG6 Register bit assignments (continued)

Bits Name Function

31 0

0 00111 0 0010001110100 0010 011000 11

DAP ROM Default Target ID

24 23 16 15 8 7

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 177 178

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