ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 92)

Programmers Model

ID062813 Non-Confidential

Test chip SCC Register 41

The CFGREG41 Register characteristics are:

Purpose Cortex-A15 configuration register 0 that enables you to read and write

Cortex-A15 configuration settings.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-19 shows the bit assignments.

Figure 3-19 Test chip CFGREG41 Register bit assignments

Table 3-21 shows the bit assignments.

31 16 15 8 0

0 10011 0 0110000000010 0011 011000

Reserved

SPNIDEN[1:0]

30 29 28 27 26 25 24 23 22 21 20 19 18 17 14 13 12 11 10 9 6 43

Reserved

SPIDEN[1:0]

NIDEN[1:0]

DBGEN[1:0]

CFGTE[1:0]

VINITHI_CORE[1:0]

IMINLN

CLUSTER_ID

Table 3-21 Test chip CFGREG41 Register bit assignments

Bits Name Function

[31:30] - Reserved. Do not modify.

[29:28] SPNIDEN[1:0] Maps to the SPNIDEN secure privileged non-invasive debug enable bus for both

Cortex-A15 cores:

Disable secure privileged non-invasive debug.

Enable secure privileged non-invasive debug.

The default is

b11

[27:26] - Reserved. Do not modify.

[25:24] SPIDEN[1:0] Maps to the SPIDEN secure privileged invasive debug enable bus for both

Cortex-A15 cores:

Disable secure privileged invasive debug.

Enable secure privileged invasive debug.

The default is

b11

[23:22] - Reserved. Do not modify.

[21:20] NIDEN[1:0] Maps to the NIDEN non-invasive debug enable bus for both Cortex-A15 cores:

Disable non-invasive debug.

Enable non-invasive debug.

The default is

b11

1 2 ... 87 88 89 90 91 92 93 94 95 96 97 ... 177 178

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