ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 89)

Programmers Model

ID062813 Non-Confidential

Figure 3-17 shows the bit assignments.

Figure 3-17 Test chip CFGEG13, 15, 17, 19, 21, 23, and 25 Register bit assignments

Table 3-19 shows the bit assignments.

31 0

000 0100010111100 10 000000000000 0

x_CLKF

Reserved

16 15

29 28

x_HARD_BYPASS

Table 3-19 CFGREG13, 15, 17, 19, 21, 23, and 25 Register bit assignments

Bits Name Function

[31:29] - Reserved. Do not modify.

[28:16] x_CLKF PLL feedback clock divider settings. Divisor = x_CLKF+1.

These bits have the following default values:

CFGREG13 - SYS PLL

b0001000101111

, decimal 559.

CFGREG15 - DDR PLL

b0000010111111

, decimal 191.

CFGREG17 - HDLCD PLL

b0000111001101

, decimal 461.

CFGREG19 - A15 0 PLL

b0001000101111

, decimal 559.

CFGREG21 - A15 1 PLL

b0001000011011

, decimal 539.

CFGREG23 - A7 0 PLL

b0001110011111

, decimal 927.

CFGREG25 - A7 0 PLL

b0_0001_FFFF_0111

, decimal 503.

See Test chip PLLs and clock divider logic on page 2-30.

Note

See Table 2-8 on page 2-28 for the maximum clock operating

frequencies.

[15:1] - Reserved. Do not modify.

[0] x_HARD_BYPASS This bit forces the reference input clock to bypass the PLL to enable

it to be driven directly into the design.

Do not bypass PLL.

Bypass PLL.

The default value is

for all control registers.

Note

The

board.txt

file sets the HDLCD PLL to bypass by setting

CFGREG17[0] to

during the configuration process. You can set

CFGREG17[0] to

if you want to use the HDLCD PLL.

ARM does not recommend using the non-default options, and

Figure 2-10 on page 2-26 does not show these connections.

1 2 ... 84 85 86 87 88 89 90 91 92 93 94 ... 177 178

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