
Revisions
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. D-2
ID062813 Non-Confidential
Table D-4 Differences between issue C and issue D
Change Location Affects
Clarified that user can access NOR Flash 0 at two
memory locations.
Overview of daughterboard memory map on page 3-3.
Table 3-1 on page 3-5
All revisions
Corrected Cortex-A7 cluster version number. Cortex-A15_A7 MPCore test chip on page 2-4
Cortex-A7 cluster on page 3-55
All revisions
Updated interrupt table. Table 2-11 on page 2-35 All revisions
Table D-5 Differences between issue D and issue E
Change Location Affects
Corrected default value of register bit
BROADCASTOUTER for MPCore A15 and MPCore A7.
Figure 3-20 on page 3-37
Table 3-22 on page 3-37
Figure 3-22 on page 3-41
Table 3-24 on page 3-41
All revisions
Corrected definition of CoreSight Debug enable register bit Table 3-11 on page 3-20 All revisions
Corrected default value of IMINLN bit in MPCore A15
configuration register 0.
Table 3-21 on page 3-35
Figure 3-19 on page 3-35
All revisions
Corrected test chip reset value of MPCore A15 configuration
register 0.
Table 3-6 on page 3-13 All revisions
Added default value of boot cluster bit in the system
information register.
Table 3-28 on page 3-48 All revisions
Added default value of boot core bits in the system
information register.
Table 3-28 on page 3-48 All revisions
Table D-6 Differences between issue E and issue F
Change Location Affects
Added description of bits[15:11] of system information
register.
Figure 3-26 on page 3-48
Table 3-28 on page 3-48
All revisions
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