ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 74)

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3.3.4 Test chip SCC register descriptions

This section describes the SCC registers. Table 3-6 on page 3-13 provides cross references to

individual registers.

Test chip SCC Register 0

The CFGREG0 Register characteristics are:

Purpose SMC CS0 and CS1 Register that enables you to read and write match and

mask bits for the SMC CS0 and SMC CS1. See Mask operation to define

SMC chip select address ranges on page 3-15.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-5 shows the bit assignments.

Figure 3-5 Test chip CFGREG0 Register bit assignments

Table 3-7 shows the bit assignments.

Test chip SCC Register 1

The CFGREG1 Register characteristics are:

Purpose SMC CS2 and CS3 Register that enables you to read and write match and

mask bits for the SMC CS2 and SMC CS3. See Mask operation to define

SMC chip select address ranges on page 3-15.

Usage constraints There are no usage constraints.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-6 on page 3-18 shows the bit assignments.

SMC_ADDR_MATCH0_1

31 24 23 16 15 8 0

0 10100 1 0000011111100 1111 100000

SMC_ADDR_MASK0_1

SMC_ADDR_MATCH0_0

SMC_ADDR_MASK0_0

Table 3-7 Test chip CFGREG0 Register bit assignments

Bits Name Function

[31:24] SMC_ADDR_MATCH0_1 SMC CS1 address match of top 8 bits

[23:16] SMC_ADDR_MASK0_1 SMC CS1 address mask of top 8 bits

[15:8] SMC_ADDR_MATCH0_0 SMC CS0 address match of top 8 bits

[7:0] SMC_ADDR_MASK0_0 SMC CS0 address mask of top 8 bits

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 177 178

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ARM AMBA NIC-301 Dokumentacja Strona 74