ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 43)

Hardware Description

ID062813 Non-Confidential

Table 2-8 shows the maximum clock operating frequencies.

Note

ARM derives the values in Table 2-8 from a random sample of test chips operating at room

temperature and from temperature testing and RTL simulations. They are the best estimate

ARM can provide on the maximum operating frequencies, but the maximum operating

frequencies of the test chip on your daughterboard might be different from the frequencies in

Table 2-8.

The daughterboard OSCCLK sources, and the PLL divider settings, control the minimum test

chip operating frequencies.

Table 2-9 shows the daughterboard OSCCLK clock sources.

Table 2-8 Cortex-A15_A7 test chip maximum clock operating frequencies

Clock Maximum operating frequency

A15_CLK 1GHz

A7_CLK 800MHz

PCLK 1GHz

TRACECLKIN 140MHz

SMB_REFCLK 50MHz

ACLK 500MHz

PXLCLK and MMB_IDCLK 165MHz

DDRCLK 400MHz

HSBM (CLK) 40MHz

Table 2-9 Daughterboard OSCCLK clock sources

Test chip signal Function Source

OSCCLK

frequency

range and default

Description, clocks derived from test chip

signal

CPUREFCLK0 A15 PLL 0

reference clock

OSCCLK 0 17MHz-50MHz

Default is 50MHz

Reference for CPU_CLK0_A15. This is the default

source for A15_CLK, the clock for the Cortex-A15

dual-core cluster.

Default CPU_CLK0_A15 to OSCCLK 0 ratio: 20:1.

CPUREFCLK1 A15 PLL 1

reference clock

OSCCLK 1 17MHz-50MHz

Default is 50MHz

Reference for CPU_CLK1_A15. This is an

alternative source for A15_CLK, the clock for the

Cortex-A15 dual-core cluster.

Default CPU_CLK1_A15 to OSCCLK 1 ratio: 20:1.

CPUREFCLK2 A7 PLL 0

reference clock

OSCCLK 2 17MHz-40MHz

Default is 40MHz

Reference for CPU_CLK2_A7. This is the default

source for A7_CLK, the clock for the Cortex-A7

triple-core cluster.

Default CPU_CLK2_A7 to OSCCLK 2 ratio: 20:1.

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 177 178

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