ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 152)

Signal Descriptions

ID062813 Non-Confidential

A.4 Debug and trace connectors

This section describes the debug and trace connectors on the daughterboard.

Caution

• Your external debug interface unit must adapt its interface voltages to the voltage level of

the daughterboard JTAG. All the trace and JTAG signals operate at 1.8V.

A.4.1 JTAG connector

The daughterboard provides the JTAG connector to enable connection of DSTREAM or a

compatible third-party debugger. Figure A-3 shows the JTAG connector.

Note

• EDBGRQ has a pull-down resistor to 0V. The daughterboard does not support adaptive

clocking and RTCK has a pull-down resistor to 0V. All other signal connections on the

P-JTAG connector have pull-up resistors to 1V8.

• Pins 7 and 9 of the JTAG connector are dual-mode pins that enable the Cortex-A15_A7

test chip to support both the JTAG and SWD protocols.

Figure A-3 JTAG connector, J6

Table A-1 shows the JTAG pin mapping for each JTAG signal.

Table A-1 JTAG connector (J6) signal list

Pin Signal Pin Signal

1 VTREFC 2 VSUPPLYA

3 nTRST 4 GND

5 TDI 6 GND

7 TMS/SWDIO 8 GND

9 TCK/SWCLK 10 GND

11 RTCK 12 GND

13 TDO 14 GND

15 nSRST 16 GND

17 EDBGRQ 18 GND

19 DBGACK 20 GND

1 2 ... 147 148 149 150 151 152 153 154 155 156 157 ... 177 178

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ARM AMBA NIC-301 Dokumentacja Strona 152