ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 77)

Programmers Model

ID062813 Non-Confidential

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

Figure 3-9 shows the bit assignments.

Figure 3-9 Test chip CFGREG4 Register bit assignments

Table 3-11 shows the bit assignments.

CORESIGHT_NIDEN

31 27 26 23 10 7 4 3 0

0000000000000000000001111010000

CORESIGHT_DBGEN

Reserved

AXIBM_REMAP

189

CORESIGHT_SPIDEN

CORESIGHT_SPNIDEN

Reserved

242528

SMC_Remap[1:0]

DMA_IRQ_NS

DMA_PERIPH_NS

DMA_BOOT_NS

DMA_BOOT_FROM_PC

Table 3-11 Test chip CFGREG4 Register bit assignments

Bits Name Function

[31:28] DMA_IRQS_NS[3:0] These bits control the security state of the interrupt outputs when DMAC exits from reset:

DMA_IRQ_NS[x] =

The DMAC assigns IRQ[x] to the Secure state.

DMA_IRQ_NS[x] =

The DMAC assigns IRQ[x] to the Non-secure state.

The default is

b0000

See the AMBA

DMA Controller DMA-330 Technical Reference Manual.

[27:26] DMA_PERIPH_NS[1:0] Boot peripherals security state. These bits control the security state of the peripheral request

interface when the DMAC exits from reset:

DMA_PERIPH_NS[x] =

The DMAC assigns peripheral request interface[x] to the Secure state.

DMA_PERIPH_NS[x] =

The DMAC assigns peripheral interface request interface[x] to the Non-secure

state.

The default is

b00

See the AMBA

DMA Controller DMA-330 Technical Reference Manual.

[25] DMA_BOOT_NS Boot manager security state. When the DMAC exits from reset, this bit controls the security

state of the DMA manager thread:

Assigns DMA manager to the Secure state.

Assigns DMA manager to the Non-secure state.

The default is

See the AMBA

DMA Controller DMA-330 Technical Reference Manual.

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