ARM AMBA NIC-301 Dokumentacja Pobierz pdf (Strona 32)

Hardware Description

ID062813 Non-Confidential

Internal resets

Test chip SCC Register 6 on page 3-22 controls the internal resets that operate independently of

nRESET. Table 2-2 shows the blocks that the internal resets control.

b. The reset request from the daughterboard results in the motherboard asserting CB_nRST.

CB_nPOR can optionally be asserted by correctly defining the value of ASSERTNPOR, that can be TRUE or FALSE in the

config.txt

motherboard configuration file. See the Motherboard Express μATX Technical Reference Manual for an example

config.txt

file.

Table 2-2 Internal resets controlled by SCC registers

Reset Core

NEON

and

VFP

Debug

PTM

ETM

Breakpoint

and

watchpoint

logic

Shared

debug,

APB, CTI

and CTM

logic

Shared L2

memory

system,

GIC and

timer

logic

Comment

A15_NCPURESET Yes Ye s Yes Yes Yes No No A15_CLK

domain.

Fine-grain

reset.

A7_NCPURESET Yes Ye s Yes Yes Yes No No A7_CLK

domain.

Fine-grain

reset.

A15_NCORERESET Yes Yes No No No No No A15_CLK

domain.

Fine-grain

reset.

A7_NCORERESET Yes Yes No No No No No A7_CLK

domain.

Fine-grain

reset.

A15_NCXRESET No Yes No No No No No A15_CLK

domain.

Fine-grain

reset.

A15_NDBGRESET No No Yes Yes Yes No No A15_CLK

domain.

Fine-grain

reset.

A7_NDBGRESET No No Yes Yes Yes No No A7_CLK

domain.

Fine-grain

reset.

A7_NETMRESET No No No Yes Yes No No

A15_NPRESETDBG No No No No N Yes No A15_CLK

domain.

Overrides

fine-grain

resets.

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